Gowin FPGA PLL Calculator

FPGA Board:

FCLKIN: MHz

IDIV_SEL:

  # PFD = FCLKIN / (IDIV_SEL+1)

PFD = 3 MHz (supported range: 3 MHz - 400 MHz)

FBDIV_SEL:

  # CLKOUT = FCLKIN * (FBDIV_SEL+1) / (IDIV_SEL+1)

CLKOUT = MHz (supported range: 4.6875 MHz - 600 MHz)

ODIV_SEL:

  # VCO = (FCLKIN * (FBDIV_SEL+1) * ODIV_SEL) / (IDIV_SEL+1)

VCO = 600 MHz (supported range: 600 MHz - 1200 MHz)

Enable CLKOUTD output signal?

DYN_SDIV_SEL:

# CLKOUTD = CLKOUT / DYN_SDIV_SEL

CLKOUTD = MHz

Verilog instantiation code: (copy-paste this in your project)

#( // For
  .FCLKIN(""),
  .IDIV_SEL(), // -> PFD = MHz (range: - MHz)
  .FBDIV_SEL(), // -> CLKOUT = MHz (range: - MHz)
  .DYN_SDIV_SEL(),   .ODIV_SEL() // -> VCO = MHz (range: - MHz)
) pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .FBDSEL(6'b0), .IDSEL(6'b0), .ODSEL(6'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0), .VREN(1'b1),
  .CLKIN(in_clk), // MHz
  .CLKOUT(out_clk), // MHz
  .CLKOUTD(out_clkoutd), // MHz
  .LOCK(clk_lock)
);